(a) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a semiconductor device having a package structure in which a semiconductor element (chip) is mounted inside a wiring board for a reduction in thickness, and relates to a method of manufacturing the same.
(b) Description of the Related Art
Heretofore, semiconductor devices having various forms have been proposed in which a chip is mounted inside a wiring board. As an example thereof, there is a package structure (semiconductor device) intended to form a required circuit block by incorporating and stacking a plurality of chips, for example, typified by System Block Module manufactured by Toshiba Corporation Semiconductor Company. In this semiconductor device, connection between upper and lower layers is established around chips. Accordingly, on the upper and lower surfaces of each package, top-and-bottom connecting pads are placed around the chip. The top-and-bottom connecting pads are used for connecting packages (chips) stacked on and under the relevant package (chip). Most of the top-and-bottom connecting pads are connected also within the relevant package. In such a semiconductor device, plated through holes have been typically used as means for connecting the top-and-bottom connecting pads within the package.
For example, as described in Japanese unexamined Patent Publication (JPP) 2001-217337, technologies relating to the above-described known technology include the following technology: multilayer stacking can be realized by burying and mounting a semiconductor chip in a package, and providing external connection terminals on both surfaces of the package or exposing, from a solder resist layer, terminal formation portions (pad portions) of a wiring pattern to which external connection terminals are to be connected.
As described above, in a known package structure (semiconductor device) adapted for the stacking of a plurality of chips using top-and-bottom connecting pads provided in a region around the chips, plated through holes have been utilized when the top-and-bottom connecting pads are connected within the package.
However, plated through holes are often formed by drilling. Consequently, the diameters of the through holes become relatively large (approximately 250 to 300 μm in the state of the art), and there has been the disadvantage in that a larger area is accordingly required. Further, there are constraints on design (i.e., the degree of freedom of wiring is low), such as a technical difficulty of placing top-and-bottom connecting pads on plated through holes. Accordingly, the relevant pads must be formed at other positions, and an area required around a chip increases. This has become an obstacle to miniaturization.
Essentially, one of major purposes in stacking chips is to enhance functionality by incorporating a larger number of functional elements (chips) into a smaller volume. However, the above-described problem becomes a serious obstacle to the accomplishment of this purpose. Namely, in a package (semiconductor device) containing a chip, a region around the chip is not a portion which exerts an essential function as the semiconductor device, but a portion used for simply connecting upper and lower stacked packages. Accordingly, in consideration of recent demands for smaller sizes, higher densities, and the like, of thin-type packages, it is more desirable that an area required around a chip is as small as possible.
On the other hand, a conceivable method of coping with the above-described problems is as follows: after a chip is buried in resin, openings are formed at predetermined positions in a resin layer on the chip by laser processing, photolithography, or the like, to form via holes, and interconnections connected to pads of the chip through the via holes are formed. However, this method has a problem of the accuracy of opening positions when the via holes are formed on the chip. This becomes more pronounced as the sizes of via holes to be formed on the chip for electrical connection decreases and as the pitch decreases.